This invention relates to integrated circuit testing systems and more particularly to a tape used as an interface between an electronic device and a test system.
Conventionally, integrated circuit devices are tested prior to dicing and packaging to determine whether defects are present. The evaluation of performance of such an integrated circuit is accomplished at various points in the manufacturing process and at the end of fabrication. In order to test such circuits, an electrical connection must be made to many of the integrated circuit's connection points. Test signals are then applied to the circuit and the performance is evaluated.
Within the art a variety of schemes have been devised for testing such integrated circuit devices. One problem is that the automated high-volume manufacturing of semiconductor wafers has advanced to the point that test apparatus must be similarly designed to handle high volumes of product to be tested. A single test station may be called upon to make thousand of tests per day. Each test requires that the contact array make and break contact to a different test site either on the same wafer or on a series of wafers in a reliable manner. The result of this test methodology is that the contact probes become worn and must be replaced frequently. The time required for replacement of a contact array removes the tester machine from operation. This adds to the cost of the semiconductor product.
Another problem is that as circuits continue to shrink it becomes increasingly difficult to perform wafer level electrical tests prior to packaging. Moreover, in the case of VLSI circuits, there is an increasing requirement for larger numbers of input and output (I/O) terminal connections. Consequently, as such circuits become increasingly complex with increased demands for I/O, the size and spacing of those I/O pads continually decreases. As the pitch reaches the order of a few mils, conventional probe systems are not available. Photolithographic techniques must be used to produce probe arrays for mil-sized pitches.
Yet another problem when using prior art systems for mil-sized pitch pads systems is the mechanical construction of the conventional probe. These systems cannot achieve high positional resolution, which may be compounded by wear and resurfacing by replanarizing techniques such as grinding. Again lithographic techniques are needed to produce the probe array.
Electrical interface problems also exist. The high number of I/O and high speeds of operation on contemporary VLSI chips increases the probability for induced noise when many off-chip drivers switch simultaneously during tests. This simultaneous switching places very vigorous demands on the electrical performance of the probe during tests. Present day schemes are very near the limits of usability, and are a source of erroneous test data. Probes must be designed to have minimum inductive coupling to reduce induced noise.
Representative of the prior art which has been used in the past for purposes of testing micro miniature components is U.S. Pat. No. 3,493,858, which relates to a flexible bag stretched over a frame having a series of conductors mounted thereon. The conductors consist of electroplated Cu, patterned by photolithography, on a mylar film. Compatibility between the terminal portions of both the flexible member and the device under test, is achieved by inflation the probe points are extended into contact with the corresponding terminal areas on the circuit.
U.S. Pat. Nos. 3,405,361 and 4,065,717 both relate to multi point probes employing flexible sheet-like members carrying probes to make contact with a semiconductor device. The pattern of the flexible sheet allows for contacts to be distributed around the member under test. This flexible member forms part of a chamber into which fluid is introduced so that it deforms and causes the probes to make contact with the semiconductor device. In the .+-.361 patent the probes formed by lithography have plated bump tips.
Techniques to take into consideration variations of the height of the pads on the device under test have also been considered in the prior art. U.S. Pat. No. 3,826,984 discloses a contact scheme having a series of cantilevered beams extending radially inward from a nonconducting support disk into a circular substrate opening. Another example of a cantilever type probe is found in U.S. Pat. Nos. 4,649,338 and 4,677,474. The contacts are allowed to deflect in the vertical direction to conform to height variations among the contact pads.
U.S. Pat. No. 3,832,632 deals with the problem of elevational differences by employing probe tips made of a compressible elastic material. An annular, cantilever design is employed.
U.S. Pat. No. 4,649,339 describes a probe with features smaller to those in the prior art above. This probe consists in a continuous flexible sheet without openings, with a series of conductive lines which fan out from a central aperture. The contacts consist of lithographically patterned Cu and the sheet is polyimide, without openings. The metal can be used on both sides of the film, creating a ground-plane controlled impedance structure. At the aperture, the lines are connected to contacts on the opposite side of the sheet. The contacts are used to form the electrical connection between the chip and connector pads. By means of a spring loaded central conductor, contact is made between terminals on the inner face and pads on the device under test. As in other prior art systems, the test probe head employs air pressure to exert the force necessary to bring the probe tips into contact with the device under rest.
Reference is made to U.S. Pat. No. 4,673,839, which also relates to a chip probe test system. This system employs a flexible probe in the form of a small square of thermal plastic polyimide film. The underside of the film includes a plurality of metal pads which are arranged in a pattern that matches the contact pads on the chip. The pads are electrically connected by the use of microstrip line geometry techniques, such as piezoelectric elements. Yet another example of a strip line for purposes of testing semiconductors is described in Japanese Laid-Open Application No. 60-260,861. An x- shape strip film having a number of connectors thereon is attached by a jig and moved into contact with a semiconductor device under test. By varying the force on the jig, the applied force to the contact terminals can be adjusted.
The above discussed art shows the use of integrally mounted probe arrays built into the tester apparatus. To the extent that a film is used with holes, such are simple round or square holes and is not continuous to provide more than one pattern on the film.
The above prior art reveals that a -myriad of techniques have been proposed for testing integrated circuit elements. All have, to varying degrees, the deficiencies noted above.